This application claims the benefit of Application No. P1999-43252, filed in Korea on Oct. 7, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly, to nonvolatile memory, in which a flash memory cell having two floating gates is provided for storing a significant amount of information per cell, and a method for sensing data therefrom.
2. Background of the Related Art
In general, there is a volatile memory which permits erasing stored information and saving new information and a nonvolatile memory which permits storing information only once. In the volatile memory, there are RAM data which are writable thereto and readable therefrom, and in the nonvolatile memory, there are ROM (Read Only Memory), EPROM (Erasable Programmable ROM), and EEPROM (Electrically Erasable Programmable ROM) data. The ROM cannot be programmed again once information is stored, but the EPROM and EEPROM an be programmed again once infonnation stored therein is erased. The EPROM and EEPROM have the same information programming operation, but different information erasing operation. The EPROM erases information stored therein using a U.V. ray, while the EEPROM erases information stored therein using electricity. Keeping pace with demands for a large-sized memory according to the development of the information industry, DRAM is the most widely used as a mass storage media. However, DRAM requires a storage capacitor above a certain size which requires periodic refreshment. Accordingly, instead of DRAM, there have been extensive studies on EEPROM which requires no refreshment. However, since EEPROM also permits writing either xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 thereon, a device packing density corresponds to a number of memory cells. Therefore, when it is intended to use EEPROM as data storage media, the greatest problem is that the cost per bit is too high. In order to solve this problem, there is active research on a multi-bit memory cell. The multi-bit memory cell permits significantly increased data storage density in the same area of a chip without reducing memory cell size by storing two or more than two data in one memory cell. The multi-bit memory cell is programmed in multiple stages of threshold voltage levels. That is, in order to program two bits of data in one cell, each of the cells should be programmed in four stages of threshold voltage levels as is known from 22=4. In this instance, the threshold levels in each cell correspond to logic states of 00, 01, 10, and 11. Accordingly, in order to increase a number of bits per cell by programming the cell in more levels, dispersion of each of the threshold voltage levels should be reduced by adjusting the threshold voltage levels precisely.
A related art nonvolatile memory, cell array thereof, and method for sensing data therefrom will be explained with reference to the appended drawings. FIGS. 1A and 1B illustrate unit cells of related art nonvolatile memory cells. FIG. 2 illustrates a cell array of related art nonvolatile memories. FIG. 3A illustrates cell states at threshold voltages according to the first related art method, and FIG. 3B illustrates cell states at control gate voltages and reference currents according to the first related art method.
The related art nonvolatile memory is flash memory, and a unit cell is provided with, as shown in FIGS. 1A and 1B, a stack of a first gate insulating film 2, a floating gate 3, a second insulating film 4, and a control gate 5 on a first conduction type semiconductor substrate 1, and second conduction type drain 6a and source 6b in the semiconductor substrate 1 on opposing sides of the floating gate 3. A channel region is formed in the semiconductor substrate 1 under the floating gate 3 when a write or read operation is performed.
Referring to FIG. 2, a cell array of related art nonvolatile memories is provided with a plurality of flash memory cells, wordlines 10, bitlines 11, sourcelines 12, and a common sourceline 13. There is a matrix of the plurality of flash memory cells each having a floating gate and a control gate, with the plurality of wordlines 10 formed in an axial direction for providing a voltage to control gates in the flash memory cells in a longitudinal direction. There is a drain contact DS for every two unit cells, and there are a plurality of the bitlines 11 disposed in a longitudinal direction, each connecting the drain contacts DS in the axial direction. And, there are a plurality of the sourcelines 12 disposed in the axial direction each connecting sources 6b of the unit cells in the longitudinal direction, and there is the common sourceline 13 disposed the axial direction.
Write, read, and erase operations of the flash memory 14 selected from the related art nonvolatile memory having the aforementioned system will be explained with reference to FIGS. 1A and 2, and TABLE 1.
Referring to FIGS. 1A and 2, in the write operation, after selecting one of the flash memory cells at a crossing point of a selected wordline 10 and a selected bitline 11, a voltage of 5xcx9c6V is provided to a drain 6a of the selected flash memory cell, a voltage of 10xcx9c12V is provided to the wordline 10, and a voltage of 0V is provided to the common sourceline 13 causing current to flow in the channel, that, in turn, causes hot electrons to migrate from the channel to the floating gate 3 through the first gate insulating film 2. Upon reception of the electrons to the floating gate 3, the flash memory cell is involved in a pull up of the threshold voltage, stopping the write operation when the threshold voltage reaches a desired threshold voltage.
Referring to FIGS. 1A and 2, in the read operation, after a voltage of 5xcx9c10V is provided to the wordline 10, a voltage of approximately 1V is provided to the bitline 11, and a voltage of 0V is provided to the common sourceline 13, current flowing through the channel is sensed, and a threshold voltage corresponding to the current is read to read stored information.
Referring to FIGS. 1A and 2, in the erasure operation, the bitline 11 is floated, a voltage of xe2x88x9210V or 0V is provided to the wordline 10, a voltage of 12V or 3.3xcx9c5V is provided to the common sourceline 13, causing electron tunneling of electrons stored in the floating gate 3 to the source 6b through the first gate insulating film 2. In this instance, a plurality of the flash memory cells connected with the common sourceline 13 can be erased at the same time, block by block. Levels of the threshold voltages in the flash memory cell can be adjusted to provide states of 2, 4, 8, or over. A cell with equal to or more than four states is called as a multilevel cell.
Next, methods for sensing cells having one bit information which have two states, and cells having two bit information, which have four states, will be explained with reference to FIGS. 3A, 3B, TABLE 2, FIGS. 4A, 4B, and TABLE 3.
When one bit information is stored, a case where a cell current is higher than a reference current is defined as xe2x80x980 statexe2x80x99 and a case where the cell current is lower than the reference current is defined as xe2x80x981 statexe2x80x99, as illustrated in FIG. 3A and TABLE 2. The cell and reference currents are a result of measuring I-V characteristics of a flash memory cell where one reference threshold voltage is set. Since writing to many flash memory cells is conducted, the states show a state as shown in FIG. 3B that provides a read allowance (a value divided by two of a value obtained by subtracting a maximum current in the xe2x80x981 statexe2x80x99 from a minimum current in the xe2x80x980 statexe2x80x99). As shown in FIG. 3B, first and second threshold voltages Vth1 and Vth2 have a distribution of xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 states, respectively. It is preferable that the read allowance is as large as possible for maintaining information in the flash memory cell, which requires narrower dispersions xe2x80x98Wxe2x80x99 of the xe2x80x980 statexe2x80x99 and xe2x80x981 statexe2x80x99 threshold voltages, with a greater difference between the dispersions. By doing this, an allowance for setting the reference threshold voltage for reading a state of information stored in the flash memory cell becomes great.
A method for reading information from a flash memory cell having two bit information stored therein will be explained. FIG. 4A illustrates cell states at threshold voltages according to a second method of the related art, and FIG. 4B illustrates cell states at control gate voltages and reference currents accordingly.
Referring to FIG. 4A, in the related art two bit information sensing, a cell current is compared to first, second, and third reference currents (the first reference current being greater than the second reference current being greater than the third reference current), to represent as a xe2x80x9800xe2x80x99 state when the cell current is greater than the first reference current, to represent as a xe2x80x9801xe2x80x99 state when the cell current is greater than the second reference current and smaller than the first reference current, to represent as a xe2x80x9810xe2x80x99 state when the cell current is greater than the third reference current and smaller than the second reference current, and to represent as xe2x80x9811xe2x80x99 state when the cell current is smaller than the third reference current. As shown in FIG. 4A, illustrating current-voltage characteristic curves, there are first, second, third, and fourth threshold voltages Vth1, Vth2, Vth3, and Vth4 in the xe2x80x9800xe2x80x99, xe2x80x9801xe2x80x99, xe2x80x9810xe2x80x99, and xe2x80x9811xe2x80x99 states, respectively. As shown in FIG. 4B, the first, second, third and fourth threshold voltages Vth1, Vth2, Vth3, and Vth4 have xe2x80x9800xe2x80x99, xe2x80x9801xe2x80x99, xe2x80x9810xe2x80x99, and xe2x80x9811xe2x80x99 dispersion states, respectively.
However, the related art nonvolatile memory and the method for sensing data therefrom has the following problems. First, in implementing a multi-bit cell in a flash memory cell, a difference of threshold voltages between states should be great for maintaining a great read allowance. The great difference of threshold voltages leads a control gate voltage higher, which increases a probability of electron leakage from a floating gate, which, in turn, causes the cell state to become unstable. Second, when a high voltage is provided to a control gate in order to obtain a greater read allowance, peripheral circuits become larger and more complicated. Third, since the storage of three bit information per one flash memory cell requires a higher control gate voltage and much time and effort to reduce dispersion of the threshold voltage, the storage of information of more than three bits is difficult.
Accordingly, the present invention is directed to a nonvolatile memory, a cell array thereof, and a method for sensing a data therefrom that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile memory, a cell array thereof, and a method for sensing a data therefrom, which can increase a read allowance of one flash memory cell, and store a significant amount of information.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the nonvolatile memory having unit cells, each unit cell includes a first gate insulating film formed on a semiconductor substrate; a first floating gate and a second floating gate formed on the first gate insulating film, the first floating gate being isolated from the second isolating gate; impurity regions formed on first sides of the first and second floating gates; a second gate insulating film formed on the semiconductor substrate inclusive of the first and second floating gates; a first control gate formed on the second gate insulating film covering a top portion and the first side of the first floating gate; and a second control gate formed on the second gate insulating film covering a top portion and the first side of the second floating gate, the second control gate being isolated from the first control gate.
In other aspect of the present invention, the cell array of nonvolatile memories includes a matrix of flash memory cells, each flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; a plurality of wordlines disposed in an axial direction and connected to the first control gates in a longitudinal direction; a plurality of distinguishlines disposed in the longitudinal direction perpendicular to the wordlines and connected to the second control gates in the axial direction; a plurality of bitlines disposed perpendicularly to the wordlines and connected to a power source contact; a plurality of groundlines disposed in the axial direction in parallel to the bitlines and connected to a ground contact; a plurality of drainlines disposed in the axial direction in parallel to the bitlines and contacting the drains in the axial direction; a plurality of sourcelines disposed in the axial direction parallel to the groundlines and contacting the sources in the axial direction; a plurality of drain selection transistors disposed between the plurality of drainlines and the power source contact; a plurality of drain selection lines disposed in parallel to the plurality of wordlines, thereby providing a drain selection signal to the plurality of drain selection transistors in the longitudinal direction; a plurality of source selection transistors disposed between the sourceline and the ground contact in the longitudinal direction; and a plurality of source selection lines disposed parallel to the plurality of wordlines, thereby providing a source selection signal to the plurality of source selection transistors in the longitudinal direction.
In another aspect of the present invention, there is provided a method for sensing a data in a nonvolatile memory, including the steps of selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing infonnation bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.